20250121_PreConF_Yee.PDF

《20250121_PreConF_Yee.PDF》由会员分享，可在线阅读，更多相关《20250121_PreConF_Yee.PDF（25页珍藏版）》请在三个皮匠报告上搜索。

1、Transform Your Vision:Create Cutting-edge Chiplets Using FoundrySamsung Foundry|January 20252HereSi InterposerLogicHBMHBMChipletTossing it over the fence doesnt work anymore.MonolithicHow do we get fromThereto3Starts withSi InterposerLogicHBMHBMPackagingGoal:Enable designers to quickly go from chip

2、to chiplet design.FoundryHow do we get fromandEnds with4The Questions you need to ask Foundry.52314Mono vs.Chiplet:Do I need a chiplet?Application&Process:The right node for the right use caseD2D&IPs:Connecting the diesPackaging:From die to package5Wrapping it all up Modules6Mono vs.Chiplets:What do

3、 I really need?17MonolithicPros:Well understood development flow,straight forward packaging;what we know and are use to.Cons:Die sizes are getting large;yields are declining;difficult to do the whole design in a single die.ChipletPros:Flexibility,re-usability,breaking up larger die size(better yield

4、s);scale functions to specific process node,managing PPA and cost better;leverage IPs across platforms(re-use).Cons:Different way of designing(learning curve-system level);more complicated design(vertical integration design and packaging).Single DieMultiple DiesMono vs.Chiplet18PPAC:Performance&Cost

5、Bandwidth(shoreline):Is it BW or data rate or shoreline between chiplets that is most critical?Latency:How critical is latency and how measuring?Serial IF(i.e.XSR/USR)vs.parallel(BoW/UCIe)Power:Differing power envelopes.Trade-offs with#of lanes vs.BW vs.throughput vs.the interfaceCost:IP licensing v

6、s.area size vs.packaging costs(2D vs.2.5D vs.3D)Design&Development ResourcesDesign Effort:Experience,expertise and resources availableDevelopment Time:Timeline and schedule;availability of IPsReuse:Is it possible to reuse the chiplet or a previous chiplet?Platform strategy.Open Chiplet or Design Ser