20250122_A-103_Mallik.PDF

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1、Extending Hardware/Software Co-Design to ChipletsYoojin Ban and Arindam MallikCompute System Architecture,imecSemiconductors are the core of deep-tech innovationsComputing power needs are exploding.increasedperformanceincreasedcomplexityreduced costreduced power4Chiplets bring a new era of opportuni

2、ty for HW-SW Co-Optimization of novel compute system architecture5Chiplet benefits in a nutshell CPUGPUVPUIOISPM.CtrlMonolithic dieM.CtrlCPUVPUGPUIOISPChiplet Heterogeneous integrationMonolithic integration of all subsystems on the same die,same process.Performance Scaling Beyond full reticles(max d

3、ie size)Architecture scaling(low to Premium)by selective assemblyComposable&reusable 3rd party chiplets SKUingShorter TTM Chiplet re-use Independent validation Decoupled steppingsHigher Yield Small die with better yield Known Good DiePPACoptimization Integration of newest IP Best process for IP6Chip

4、lets for HPC/AIKey Attributes:Performance driven functional partitioning to break memory wall problemEnabling Scale-up to datacenter levelExisting chiplet-based systemIntel Ponte Vecchio47 chiplets 2330 mm2total100 billion transistorsHPCAMD EPYC MI30013 chiplets146 billion transistorsServerIntel Met

5、eor LakeConsumerApple M1-UltraConsumerDie disaggregation driversPerformance beyond reticleOptimize yield&costOptimize internal scaling portfolioChiplet as extension of SoC product/design flowOptimize interconnect per application(CHI/BoW)8Future Processing UnitsTimeEnabling the next breakthrough in p

6、erformanceSystemPerformance2024Graphics Processing UnitsCompute Processing UnitsHW SW TECH Co-design+Architectural&Technological InnovationRealized SystemsUnrealized Systems9PERFORMANCE SCALINGHPC+AI application development challengesFocus on functionality Algorithm optimization Shared memoryFocus o