闪存芯片实现及应用.pdf

1、Chiplets with eFlash IPPresenter:DK ChengSST/Microchip R&D CAD OrganizationChiplets with eFlash IPDK ChengSr.Manager/SST/Microchip R&D CADCHIPLETS AND ADVANCED PACKAGING/PHOTONICS100%of top 10 MCU makers use SST SuperFlash3Source:Statista 2024Over 200B devices have shipped from our licensees using S

2、ST SuperFlash.The current run rate exceeds 15B devices/year.SuperFlash is the leader in embedded flash technologiesSince SSTs founding in 1989,SuperFlash Technology has evolved through 4 generationsESF1:Non-self-aligned cell,with select gate doubling as erase gate30 years of volume productionESF2:Se

3、lf-aligned cell,with select gate doubling as erase gate20 years of volume production.ESF3:Self-aligned cell,with separate select gate,coupling gate,and erase gate16 years of volume production.ESF4:Self-aligned cell,with separate select gate and erase gateautomotive grade 28nm qualified and in risk p

4、roduction.All generations maintain the same E/P mechanisms and reliability advantages.They are widely used in Smart card,general-purpose MCU automotive standalone NOR 4 Generations of SuperFlashAdvanced ESF3 Technology RoadmapESF3/4-28 HKMGESF3-28 Poly/SiONESF3-22 HKMGIn productionIn development/qua

5、lificationForecastESF3-40 Gen2 ESF3-12 nm FinFET HKMGESF BCD Technology Roadmap130nm 30V130nm 85V55nm 30V55nm 16-120V 65/40nm 24-120V 28nm 24V 120V110nm 40V 180nm 20120V 130nm 40V-120V In productionIn development/qualificationForecastESF1 LMCSST Product Offerings&End Markets2.5D RDL Fan OutUse RDL(R

6、edistribution Layer)to fan out the chip.Small form-factor,driven by mobile,5G application.In mass production for years.DECA has 600mmx600mm panel process for production.3D Hybrid BondingChip-to-Chip,both have active devices;Nearly Monolithic Integration;CMOS Image Sensor,Sony HBM;AMD V-CacheESF3 Chi