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AI平台中PCIe 5和PCIe 6的混合使用:优势与挑战.pdf

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1、Mixing PCIe 5 and PCIe 6:System Design ChallengesAstera LabsMixing PCIe 5 and PCIe 6 System Design ChallengesCaleb ShetlandApplications Engineer/Astera LabsSERVERCapture the bandwidth benefit of PCIe 6 now.No need to wait for the whole ecosystem to move to PCIe 6.Leverage existing install base of PC

2、Ie 5 equipment.Enjoy wide choice,rich inventory,short lead times of mature PCIe 5 ecosystem.Future-proof the system design:swap out PCIe 5 components for PCIe 6 when available.Achieve optimal performance by matching total bandwidth across data rates.Benefits of mixing PCIe 5 and PCIe 6Smart Fabric S

3、witchPCIe 5 HostPCIe 6 HostPCIe 5 EndpointPCIe 6 EndpointPCIe 5 EndpointORThere is no“safe road”.Continuing to do what we did in the past is not adequate.Rigorous analysis and thorough system validation are the only way to navigate the PCIe 5 to PCIe 6 change successfully.When designing for mixed-mo

4、de PCIe 5 with PCIe 6,system designers need to pay more attention to EP feature set and requirements than previously.PCIe 5 host with both PCIe 5 and PCIe 6 EPs will remain a common configuration for multiple design cycles.Today well highlight 3 examples of areas where we see a need for system desig

5、ners to focus.Unprecedented change from PCIe 5 to PCIe 6FM:Requester segment in OHC-C.FM:Completer segment in OHC-A5.Segments dont exist in NFM.officially.PCIe 5 hosts dont know about PCIe 6 segment definition.However,in some cases they have their own,potentially incompatible,implementation of segme

6、nts.Legacy self-enumerating solutions need extra scrutiny.Consider the case where a PCIe 6 switch is self-enumerating.System designers should PREVENT PCIe 6 EPs from capturing a segment ID if the host is PCIe 5.Segmentssystem designers should focus on:Ensuring that PCIe 6 devices are prevented from

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根据文章内容,以下是全文关键点的概括: 1. **混合使用PCIe 5和PCIe 6的优势**: - 现在即可享受PCIe 6的带宽优势。 - 无需等待整个生态系统迁移到PCIe 6。 - 利用现有的PCIe 5设备基础。 - 享受成熟PCIe 5生态系统的广泛选择、丰富库存和短交货期。 - 系统设计未来化:当PCIe 6组件可用时,可替换PCIe 5组件。 - 通过匹配总带宽实现最佳性能。 2. **设计挑战**: - PCIe 5到PCIe 6的过渡需要严格分析和系统验证。 - 系统设计者需要更关注端点(EP)的功能集和需求。 - PCIe 5主机配置中同时包含PCIe 5和PCIe 6 EP将是常见配置。 3. **重点关注领域**: - 防止PCIe 6设备在PCIe 5主机上使用段ID。 - 加强重放机制和排序规则的交互验证。 - 强化性能监控和诊断,特别是在FM/NFM边界。 4. **性能问题生命周期**: - 在开发阶段识别性能问题。 - 使用中断驱动的遥测来捕捉间歇性问题。 - 与端点供应商合作进行固件更新。 5. **额外关注点**: - FM/NFM转换的边缘情况。 - PCIe 5.0到6.0生态系统的快速变化。 - 端点功能集的变化。 - NRZ与PAM-4信号恢复。 - IDE和FM/NFM限制。 - 速度不匹配:GPU/NIC。 - 毒化TLP处理的变化。 - 将前缀转换为OHC。 - Flit打包规则违规。 - Flit开销:更大的CRC、FEC和带宽影响。 - PCIe 5/6边界上的错误处理。 - 共享FC信用额度。 - 14位标签。
PCIe 5/6混用挑战 系统设计新挑战 PCIe 5/6混合模式要点
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