拓展前沿：芯片组设计的异构集成.pdf

1、Extending the Frontier:Heterogeneous Integration of Chiplet DesignsCT Kao,PhDProduct Engineering Group Director Cadence Design SystemsExtending the Frontier:Heterogeneous Integration of Chiplet DesignsCT Kao,PhDProduct Engineering Group Director Cadence Design SystemsCHIPLETS AND ADVANCED PACKAGING/

2、PHOTONICSOutline4321Moores Law and Heterogenous Multi-chiplet DesignChallenges in Multi-chiplet Architectures Technological Innovations and SolutionsIntegration of Design Flows in a 3D-IC Platform 2023 Cadence Design Systems,Inc.All rights reserved.4Moores Law Began Slowing Down Over a Decade AgoSou

3、rce:Karl Rupp microprocessor trend data50 Years of Microprocessor Trend DataFrequency(MHz)Typical Power(Watts)107106105104103102101100197019801990200020102020YearSingle-ThreadPerformance(SPECint x 103)Transistors(thousands)Number ofLogical CoresObligatory Moores law slowdown slide needed for all chi

4、plet presentations 2023 Cadence Design Systems,Inc.All rights reserved.5Advancing System Performance Beyond Moores LawEUVGAA2nm1nmChiplet based designs Buzz about the full potential of 3D-IC2010204020302020 2023 Cadence Design Systems,Inc.All rights reserved.6The Need for Chiplets and 3D Heterogenou

5、s IntegrationCost,YieldReticleLimitForm-FactorAnalog,IO,MemoryFlexibilityPhysical limitation on die sizePoor yields for large die size designs Adds to the costSize&Form factor limited applications Not able to utilize the full benefit of advanced nodesHeterogenous Integration-Mix and Match provides a

6、n optimal and flexible solution 2023 Cadence Design Systems,Inc.All rights reserved.72012Technology Development in Semiconductor Packaging Enabling Chiplet-Based Architectures2.5D-IC(Silicon/RDLInterposer)SiliconStacking20102020Ultra-High-DensityRDL(FOWLP)201819902022Co-Packaged OpticsSystem in Pack