利用通用芯片互连高速接口 (UCIe) 实现下一代计算的即插即用芯片创新.pdf

1、Innovations with Plug-and-Play Chiplets for Next Generation Computing using Universal Chiplet Interconnect Express(UCIe)OrganizationInnovations with Plug-and-Play Chiplets for Next Generation Computing using Universal ChipletInterconnect Express(UCIe)Debendra Das SharmaIntel Senior Fellow,Intel Corp

2、orationCHIPLETS AND ADVANCED PACKAGING/PHOTONICSOutline54321Interconnects:An important pillar of computeUCIe:An Open Standards OrganizationUCIe:Planar and Vertical Chiplet InterconnectsKey Metrics and Usage Models of UCIeFuture Directions for UCIeInterconnects:Taxonomy,Characteristics and TrendsProc

3、essorLoad-Store I/O:from die/package/node to rack/pod.PCI-Express and CXL are established standards at board level data move,coherency,memory need to leverage those for on-packageNetworking/Fabric for Data Center ScaleLatency Tolerant(Narrow,very high speed)112 GT/s-224 GT/s 4-8 lanes,cables/backpla

4、ne PHY latency(Tx+Rx)=20+ns(+100 FEC)PCIe/CXL/SMP Coherency PCIe PHY)Node(-Rack)Latency Sensitive(Wide,high speed)128 GT/s-256 GT/s Hundreds of lanes Power,cost,Si-area,backwards compatible,latency,on-board-cables/backplanes PHY latency(Tx+Rx:PHY-PIPE)=10ns(0-1ns FEC overhead)Universal Chiplet Inter

5、connect express(UCIe)TM:Die-to-DieUber Latency Sensitive(Super-wide,high speed)4-32G(very simple circuits),2D,2.5D,3D Tens of thousands of Lanes Ultra low power,ultra low latency,high bandwidth density PHY latency(PHY Transaction Layer)=better yieldReduces IP porting costsLowers product SKU costBesp

6、oke solutionMix-and-match with a standard interfaceScales innovation(Mfg.process locked IPs)Motivation for UCIeIndustry momentum behind UCIe!Package is the new platform!UCIe is the open innovation slot!UCIe ConsortiumUCIe Planar 2D and 2.5DLayered Approach Layered Approach-industryindustry-leading K