高效、安全的基于云的分裂逻辑综合.pdf

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1、Efficient and Secure Cloud-based Split Logic SynthesisChaitali Sathe,Yiorgos Markis and Benjamin Carrion Schaeferchaitali.satheutallas.edu,yiorgos.makrisutdallas.edu schaferbutdallas.edu30thAsia and South Pacific Design Automation ConferenceASP-DAC 2025Department of Electrical and Computer Engineeri

2、ngJanuary 21,2025,Tokyo Introduction What,why and how Commercial vs.open-source logic synthesis tools Security analysis Proposed flow Composed of 4 main phases Experiments Experimental setup Experimental results Conclusion2OutlineWhatEfficient(low overhead)and secure(cannot be reverse engineered)spl

3、it logic synthesis methodologyLocal:Free open-source logic synthesizer(Yosys)Cloud:Expensive commercial logic synthesizer(Synopsys DC)WhyCloud-based VLSI design environments have emerged as cost-effective solutions for VLSI design companies.E.g.,DARPA Toolbox,Synopsys(Open Link),Cadence cloudBUTDesi

4、gn companies do not trust these environmentsHowIntroductionIP vendor(.v/.vhdl)Free/inexpensive EDA tools(e.g.,Yosys)Local EnvironmentCloud Commercial EDA tools(e.g.,Synopsys Design Compiler/Ultra)RTL(.v/.vhdl)Gate netlist Yosys vs.Synopsys Design Compiler4Motivation Commercial vs.Open-source Logic S

5、ynthesistechlibLS(lib,db)1-bit+,2-bit+,4-bit mulOutputLogic synthesis script,constraintsLogic SynthesisCommercial Logic Synthesis Open-source Logic Synthesis gatenetlist commercialArea,delay reportsgatenetlist opensourcelArea,delay reportsRTL primitivesCompare resultsPrimitives area and delay differ

6、encesInput=Observation 1:Commercial HLS tools generate very optimized arithmetic circuits(addsub64u,mul16).Especially true in timing constraint synthesisObservation 2:Negligible differences when synthesizing non-arithmetic combinational circuits(xor64,nand64)Observation 3:These observations translat