AHS：用于敏捷芯片前端设计的 EDA 工具箱.pdf

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1、AHS:An EDA Toolbox for Agile Chip Front-end DesignTutorial ASPDAC 2025Jan 20,2025https:/ericlyun.me/tutorial-aspdac2025/Peking UniversityASPDACTeamYun(Eric)Liang Peking University2Tutorial ASPDAC 2025Yun(Eric)Liang ProfessorSchool of EECS/Integrated CircuitPeking URuifan Xu4th year Phd StudentFacult

2、yStudentsYouwei Xiao3rd year Phd StudentZizhang Luo3rd year Phd StudentFan Cui1st year Phd StudentXiaochen Hao5th year Phd StudentKexing Zhou1st year Phd StudentScheduleYun(Eric)Liang Peking University3TimeAgendaPresenter50minsOverview of AHSYun LiangHands-on Session45minsHigh-level Synthesis(ICCAD2

3、2,FCCM23,MICRO24)Ruifan Xu and Xiaochen Hao20minsHardware Simulation(MICRO23)Kexing Zhou45minsHardware Description Language(FPGA24)Youwei Xiao and Zizhang Luo20minsLLM-based Chip Design(ICCAD24)Fan CuiTutorial ASPDAC 2025Outline Overview Hardware design background Methodologies of AHS Hands-on Sessi

4、onYun(Eric)Liang Peking University4Tutorial ASPDAC 2025Hardware are DiverseProcessors/SoCs General-Purpose AcceleratorsDomain-specific AcceleratorsApplication-specific AcceleratorsGPUsNvidia V100AMD RX6000Open-SourceOpenCL Compatible RISC-V GPGPUML/DLTVM-VTAXilinx AlveoExample Applications:SpMV,SpMM

5、,SLAMMarkov Chain Monte CarloYun(Eric)Liang Peking UniversityTutorial ASPDAC 20255Chip Design ComplexityYun(Eric)Liang Peking UniversityOracle SPARC M7 10B transistorsIntel Haswell-EP Xeon E5 7B transistorsApple A11 4B transistors NVIDIA V100 Pascal21B transistorsIntel/Altera Stratix 1030B transisto

6、rsIBM Power9 8B transistorsApple M1 57B transistorsXilinx VU9P 35B transistorsCerebras WSE-2 2.6T transistorsTutorial ASPDAC 20256Verification is more Complex For hardware design,verification is necessaryVerification Cost Design CostCaseTechDaysA7nm47 DaysB7nm61 DaysC7nm43 DaysHardware SimulationHi-