采用 14 nm FinFET 技术自动布局生成框架生成的 500 MS丨s 8 位 SAR ADC.pdf

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1、1A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Frameworkin 14-nm FinFET TechnologyASP-DAC 2025University Design ContestYunseong Jo,Taeseung Kang,Jeonghyu Yang,and Jaeduk HanDepartment of Electronic EngineeringHanyang University,Korea2Table of ContentsMotivationAutomated Layo

2、ut Generation FrameworkSAR ADC Building BlocksLayout GenerationMeasurement ResultsConclusion 3MotivationAdvanced technology nodesIncreased design rule&sign-off flow complexityHigh human&time resources requirementHigh cost in custom layout design process Need automated layout generation!Synopsys4Auto

3、mated Layout Generation FrameworkLAYGO2Gridded object-based layout generation framework 5SAR ADC Building BlocksSAR ADC architectureCDAC,comparator,track&hold,and switching logic6Layout Generation(1/3)CDAC layoutSoftware-Defined Template(UserDefinedTemplate)for MOM capacitorGrid-based placement and

4、routingLayout Generation(2/3)Comparator layoutSoftware-Defined Template(UserDefinedTemplate)for transistorsGrid-based placement and routing7Layout Generation(3/3)Track&hold,switching logic layoutWrapper Template(NativeInstanceTemplate)for manual structuresEfficient area with hand-crafted layout8Phys

5、ical Informationlibname=mylibcellname=mycellbbox=0,0,200,100pins=p0,p1,p2,p3Hand-crafted Layout9Measurement ResultsGenerated SAR ADCFabricated in 14-nm FinFETOccupies 4,131 um2500 MS/s with 8-bit resolutionCDACSwitching LogicComparatorT&H54 um76.5 um10ConclusionAutomated layout generation in advanced technology nodesEssential for addressing increasing complexity in custom designsSAR ADC layout generation with LAYGO2Grid-based placement and routingCustomizable template for each building block Foundation for enhanced design efficiency Layout mismatch mitigation&Layout p