标准单元布局生成和设计技术协同优化的自动化.pdf

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1、Automation Automation of Standard Cell Layout Generation and Design-Technology Co-optimizationTaewhan Kim,Seoul National UniversityTOTORIAL,ASP-DAC2025 Tokyo,January 20,2025 Content1.Auto-generation of standard cells Design and technology co-optimization(DTCO)Problems Algorithms Multi-row cells Plac

2、ement legalization2.Multi-bit flip-flop(MBFF)cells Structure DTCO flow with MBFF cells DTCO techniques with MBFF cells3.Complementary FET(CFET)cells FEOL and BEOL Backside interconnect CFET vs.Flip-FET(FFET)4.ConclusionContent1.Auto-generation of standard cells Design and technology co-optimization(

3、DTCO)Problems Algorithms Multi-row cells Placement legalization2.Multi-bit flip-flop(MBFF)cells Structure DTCO flow with MBFF cells DTCO techniques with MBFF cells3.Complementary FET(CFET)cells FEOL and BEOL Backside interconnect CFET vs.Flip-FET(FFET)4.ConclusionDTCO/STCODTCO(design technology co-o

4、ptimization)Optimizing the process technology and chip design together to improve performance,power efficiency,transistor density,and cost.DTCO for a new technology node involves substantial architectural innovation rather than just delivering the exact same structure as the previous generation,just

5、 simply smaller.STOC(system technology co-optimization)Optimizing the the packaging technology and chip design together.STCO is essential to develop the advanced integration technologies for emerging systems.STCO is required to comprehend not only integration technology,circuits,architectures and so

6、ftware but also their interactions with the power delivery,cooling and system costs.DTCO/STCOManufacturingPlanar-FET,FinFET,NSFET,CFET,2D/1D metals,DRsTarget design(PPAC goals)Cells:SR/MR,min-area,min-delay,min-power,max-yield,pin accessRTL-to-GDSII TSMCs DTCO More fins Faster,but more powerReduced