基于 MFS 的 VLSI 电路高效超图建模及其仿真加速.pdf

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1、Efficient Hypergraph Modeling of VLSI Circuits for Efficient Hypergraph Modeling of VLSI Circuits for MFS-Based Emulation and Simulation Acceleration MFS-Based Emulation and Simulation AccelerationJiahao Xu,Chunyan Pei,Shengbo Tong,and Wenjian YuDept.Computer Science&Tech.,BNRist,Tsinghua University

2、,Beijing,ChinaOutline Background&Motivation Problem Formulation Adaptive Flattening Clock Modeling Evaluations Background&Motivation Problem Formulation Adaptive Flattening Clock Modeling EvaluationsIntroduction Multi-FPGA system(MFS)is widely employed for logic emulation and simulation acceleration

3、.The capacity of a single FPGA is relatively limited.How to effectively partition and map the circuit netlist into MFS is of concern.Hypergraph Partitioning The netlist is converted to abstract hypergraph first.Hyperedges in hypergraph can have more than two vertices.Hypergraph partitioning is NP-ha

4、rd.Multilevel Partitioning Engine The multilevel framework consist of three main phases:Coarsening,Initial Partitioning,Refinement.Background&Motivation Problem Formulation Adaptive Flattening Clock Modeling EvaluationsProblem Formulation Multiple Constraints Mainly,the total resources occupied by v

5、ertices assigned to a single block cannot exceed a threshold(better if balanced).can be a vector to represent different resources.Other constraints:fixed vertex constraint,grouping constraint,interconnection constraint,topology constraint.Problem Formulation Cutsize A most important optimization obj

6、ective.Edge weight*Number of blocks being assigned to.Drain nodesSource nodesEdge weightHypergraph Modeling VLSI circuits are usually designed in a hierarchical manner.Flattening the hierarchical netlist is the first task of the hypergraph modeling.Observation:Leverage the hierarchical information.K