内存内置自测试 (MBIST)：SoC 设计和验证的高级技术.pdf

《内存内置自测试 (MBIST)：SoC 设计和验证的高级技术.pdf》由会员分享，可在线阅读，更多相关《内存内置自测试 (MBIST)：SoC 设计和验证的高级技术.pdf（57页珍藏版）》请在三个皮匠报告上搜索。

1、Memory Built-In Self-Test(MBIST):Advanced Techniques for SoC Design and VerificationASPDAC 2025Prashant SeetharamanSiemens EDA1Agenda1Introduction to memory testing2MBIST fundamentals3MBIST Integration in SoC Design flow4Advanced MBIST techniques5Emerging trends and future directions6Q&A and Discuss

2、ion2Introduction on memory testing3Memory structure and operationKey takeaway:Performance considerations b/w access patterns,timing requirements and power optimization Important to understand the main features of embedded memories that have an impact on their testability and design of MBIST logic.SR

3、AM is most common case of embedded memoryTwo variations include:single port and multi port memory.4RAM bit cell structureRAM cell composed of 6 transistors4 transistors are connected as cross-coupled inverters to form a latch holding the cell valueP-channels P1 and P2 are weak as they are only used

4、to stabilize the cellN-channels N1 and N2 are strong as they are used to quickly discharge bitlines during read operationsBoth N-channel access transistors N3 and N4 are turned on when the wordline is active Source:“Digital Integrated Circuits:A Design Perspective by Jan M.Rabaey et al5Key Takeaway:

5、By optimizing transistor strengths and ratios,designers achieve a reliable memory cell capable of high-speed operations with minimal noise and power overhead Array of bit cellsData sent to and read from bit cells using differential signaling over bitlines for higher performanceData=1 if voltage of B

6、L+BL-Data=0 if voltage of BL+BL-Write operation Read operationSequence of BL+and BL-have an impact on test data patterns to applySource:“Digital Integrated Circuits:A Design Perspective by Jan M.Rabaey et al6Key takeaway:Through techniques like differential signaling,precise precharge,and robust sen