基于 Emag-Aware ML 的高速 IC 设计布局优化.pdf

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1、Emag-Aware ML-Based Layout Optimization for High-Speed IC DesignGarth Sundberg,Ph.D.Sr.Principal Engineer Ansys,Inc.Rodger Luo,Lead Engineer Ansys,Inc.2OverviewSignal integrity challenges and solution of high-speed IO designOverview of memory read and write circuit using a single bumpTraditional des

2、ign approach and the drawbacksProposed design approach using machine learning and the benefitsReview of layout and circuit to be co-optimizedResults of optimizationScaling to larger designsSummary3SI Challenge with High-SpeedIO DesignParasitic capacitance(CL)limits bandwidth and eye opening-Electros

3、tatic Discharge(ESD)protection-Solderbump pad and interconnect-Input capacitance of next stageCapacitance must be compensated forTektronix pioneered T-coil use in 1940s,and the T-coil moved on die around 1990sT-coil advantages-Large bandwidth-Small size means low loss and high-densityRDVDDCLVinVoutL

4、1RDVDDCLVinVoutL2CBLM4Bidirectional PadFor memory,data typically written and read from same padESD typically included in circuitAdd T-Coil to compensate for:-Pad capacitance-ESD-Load of receiverDesign degrees of freedom-Sign of coupling factor-Magnitude of coupling factor-Value of L1,L2,and CBVDDPAD

5、EnableDOUTVDDVDDDINDriverReceiverESDBump PadVDDPADEnableDOUTVDDVDDDINL2CBL1LMT-Coil5Present Design FlowDecide on values of L1,L2,CB,and sign/value of mutual inductance(LM)-Selected with SPICE analysis to minimize loss and/or maximize height of eye diagramSynthesize geometry by either:-Electromagneti

6、c expert designs custom T-coil manually with EM tool such as RaptorX or HFSS-Use automatic T-coil synthesis tool like VeloceRFVerify T-coil performance with SPICE analysis to confirm goal is achievedIterate this loop until goal is reached6Drawbacks With the Present Design FlowRequires hard-to-find e