下一代Chiplet的先进封装技术与设计方法.pdf

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1、2025 Rapidus Corporation.All rights reserved.Advanced Packaging Technology and Design Methodology for Next Generation ChipletsASP-DAC 2025Jan/23/2025Hideki Sasaki,Ph.D.3D Assembly Design DepartmentRapidus Corporation2025 Rapidus Corporation.All rights reserved.Outline21.Chiplet Package Requirements

2、Driven by Big Data2.Roadmap of Chiplet Packages 3.Design Considerations for Chiplet Packages2025 Rapidus Corporation.All rights reserved.13Chiplet Package Requirements Driven by Big Data2025 Rapidus Corporation.All rights reserved.New Natural ResourceBig Data42025 Rapidus Corporation.All rights rese

3、rved.HW Requirement:Higher Data Transfer Rate519902000201020202030LogicLogicMemoryConventional PKGMemoryMem.LogicData Transfer RateMemoryLogic LogicMem.Advanced PKGAllows higher data transfer rate by shortening the distance btw logic and memories.20 x10 x10 x50 xMulti tasksLarger cash memoryMulti-co

4、re CPUDDRPCIeLPDDRPKGHBMSource of Photos:AMDSource of Photos:AMD2025 Rapidus Corporation.All rights reserved.Evolution of Semiconductor Packages62D PKG2.5D PKG3D PKGIncrease interconnect layersHBMLogicSi InterposerSemi.ChipOrganic SubstratePKGStacked Logic on Logic,or SRAM on Logic,etc.Source of Pho

5、tos:AMD2025 Rapidus Corporation.All rights reserved.In an Era When PKG Determines Performance7Front-endMiniaturization of Tr.PerformanceBack-end(PKG)Integration with ChipsPKG determines performanceTo bring out performance of advanced node transistors,chips should be integrated into advanced package.

6、Performance2025 Rapidus Corporation.All rights reserved.28Roadmap of Chiplet Packages 2025 Rapidus Corporation.All rights reserved.9Big Waves on Advanced Packaging Technology MCM(1992-)-SiP(2001-)-Chiplet(2019-)Si Interposer(2006-)-RDL(2011-)-Hybrid Bonding(2020-)Source:ECTC Data base by IEEE Xplore