LLSM：具有 EDA 引导的 CoT 提示、混合嵌入和 AIG 定制加速的 LLM 增强逻辑综合模型.pdf

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1、LLSM:LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting,Hybrid Embedding and AIG-tailored AccelerationShan Huang*,Jinhao Li*,Zhen Yu,Jiancai Ye,Jiaming Xu,Ningyi Xu,Guohao Dai*Equal contributionShanghai Jiao Tong UniversityCorrespondence to:Guohao Dai ASP-DAC 2025OutlineOutlinePage 2Ba

2、ckgrounds and MotivationsRelated WorksChallenges and Techniques Overview EDA-guided CoT Prompting Text-Circuit Hybrid Embedding EDA-Tailored Acceleration Experiment ResultsExtension WorksElectronic Design Automation(EDA)Electronic Design Automation(EDA)Page 3Spec/ArchitectureDesignLogicDesignPhysica

3、lDesignSign-offMem.UnitComuteUnitCtrl.UnitCtrl.UnitCom.UnitMem.UnitLogic optimization&Map to a netlistPlacement&RoutingRTL codewritten byengineersTapeoutVerify functionality&manufacturabilityEDA refers to the use of EDA software tools to complete the functional design,synthesis,verification,physical

4、 design of VLSI chips.Key objective:Optimize the Power,Performance,Area(PPA)of the listplaceImportance of logic synthesisImportance of logic synthesisPage 4 Logic synthesis is time-consuming(50%)and has high capital cost(55%)in EDA process.TimeCost of capitalQualification of IP（26%，45%）Logic Synthes

5、is（RTLNetlist）（50%，55%）Physical Design（NetlistTapeout）（21%，56%）RTL DesignArch Design1 https:/ proportion，cost proportion）startend100%LogicLogicSynthesisSynthesisPage 5Logic synthesis is iterative in chip design.Predicting synthesis results can reduce iteration overhead.Fast,including syntax parsing,

6、design checking,etc.(15%)Slow,extensive heuristic processes(50%)Slow,further optimization(35%)Iter.SlowReduced circuit depthImport process library filesRTLCodeTraditional logic synthesis flow AI-assisted logic synthesis flow 1.Translation2.Logicoptimization3.Process mapping+PPAResultPPAResultAIModel