MetRex：使用 LLM 进行 Verilog 代码度量推理的基准.pdf

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1、MetRex:A Benchmark for Verilog Code Metric Reasoning using LLMsManar Abdelatty,Jingxiao Ma,Sherief RedaBrown University,Providence,RIhttps:/ PPA Estimation Of Verilog DesignsMotivation:Provide designer with early feedback on the quality(power,performance,area)of their designs by avoiding expensive s

2、ynthesis time.RTLFaster Design Cycles Architectural Choice TradeoffsRTL Style 1RTL Style 2RTL Style 3RTL Style 4Is my RTL Area efficient?21 P.Sengupta,et al.How Good Is Your Verilog RTL Code?A Qauick Answer from Machine Learning,2022 IEEE/ACM International Conference On Computer Aided Design(ICCAD),

3、San Diego,CA,USA.2 Fang,Wenji,et al.MasterRTL:A Pre-Synthesis PPA Estimation Framework for Any RTL Design.2023 IEEE/ACM International Conference on Computer Aided Design(ICCAD).IEEE,2023.Previous Work:Metric Estimation Using Machine LearningTotal Input BitsTotal Output BitsTotal Logic Op.BitsTotal A

4、dder/Sub Bits.Average Tree depthAverage Tree widthFeature Vector#of ANDS#of ORs#of XORs#of NOTs#of MUXSequential AreaCombinational AreaFeature Vector12Abstract Syntax Tree(AST)Simple Operator Graph(SOG)Input:RTL Code Post synthesis Metrics(Area,Delay,Power)PredictRTL Code Input:Feature Vector Output

5、:Post-synthesis MetricsPreprocessPredict3Previous Work:Metric Estimation Using Machine Learning4Intermediate Formats:Have to convert RTL code to intermediary format like Abstract Syntax Tree(ASTs)or Simple Operator Graphs(SoG).Manual Feature Extraction:Extract manually engineered features from the i

6、ntermediate format;extracted features constitute the input to the ML model.What LLMs Could Offer?Process RTL code directly(a lossless representation):InputAfter synthesis the design will have.Thus total are will be 12.0-Eliminate the need for manual feature extraction and conversion into intermediar