RISC-V系统的高效调试和跟踪：一种硬件 软件协同设计方法.pdf

1、Efficient Debug and Trace of RISC-V Systems:a hardware/software co-design approach Unrestricted|Siemens 2025|Siemens Digital Industries SoftwareOana Lazar,Embedded Software Engineer,Tessent Embedded Analytics RISC-V Summit Europe,15thMay 2025Highly efficient traceAgendaUnrestricted|Siemens 2025|Siem

2、ens Digital Industries SoftwareHardware/software co-design approachHighly efficient traceMinimally intrusive logging of program flowMinimally intrusive logging of program flowHarnessing hardware/software benefitsHarnessing hardware/software benefitsSystem integration verification for an end-to-end d

3、ebug and trace solutionIncreased complexity brings increasingly complex issuesUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareSystem complexity Generative AI High-performance computing Multi-chiplet technologies Silent Data Corruption&Heisenbugs Existing solutions interfere with sensiti

4、ve bugs More in-depth visibility is neededSkillsshortageBugcomplexity Non-intrusive solutions to facilitate debugging More visibility for multiple debug methods and insights Minimize ramp-up:use existing freeware&open-source solutionsHardware/software co-design approachUnrestricted|Siemens 2025|Siem

5、ens Digital Industries SoftwareHardware IPRun controlOn-chip traceEfficient loggingFast ELF uploadsComms.Wired comms between SoC and host machineSoftware interfaceHost software to configure hardware IP and connect with users debugging environmentsUser environmentCompatibility with debugging toolRISC

6、-V systemAXI bus/NoCSystem MemoryDebug Transport ModuleTrace interfaceHartDesigning the hardware with software in mind,and vice-versaHighly efficient traceUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareTrace decoding and reconstruction:Performed out-of-box with GDB Custom instructions