RISC-V 开放设计以及对硬件安全研究和开发活动的贡献.pdf

1、RISC-V SUMMIT 2025RISC-V open designs and contributions to hardware security research and development activitiesAgence Nationale de la Scurit des Systmes dInformation(ANSSI)11 MARS 20251212/05/2025Technical challengesImplement hardware-based security functions Performances optimization,SWaP and secu

2、rity balancing(mobility,sustainability)Early stages,protection of the cores,techno specific propertiesImprove the level of assurance Improvement of tools for security proof verification Control the design and the configuration of the security functionsSecuring the software Mechanisms securing the so

3、ftware implementation Support the increase in the size and complexity of systemsSecure Hardware FoundationTightly coupling of hardware and software securitySecure by design312/05/2025Security featuresSecure ElementsSystem on chipsIoTSmartcardsSmartphonesHSMSecure communicationsSecure computingWallet

4、sSide channel attacksFault injectionsMicro-architectural attacksArchitecturesSWaP-CSupply ChainIndustrializationCoreSecure bootMemory protectionControl flow integrityPipeline protectionPMP/MMUCrypto acc.Buses&interconnectFirewallAccess controlSecure partitioningPeripheralsIOPMP/MMUWorldguard/TEECryp

5、to coproc.TRNG/Performances/Hardware attacksTechno specificDesign specific412/05/2025 but there are many other project to which ANSSI does not contribute directlySome current activities or topics of interest Survey and technical analysis Core security functions:CVA6,CV32E40S,Ibex(Secure and CherIoT)

6、,Caliptra Secure SoC design:OpenTitan,Caliptra Tools:ArchiFI Collaborations Hardware accelerator with the IP ECC Hardware resources sharing for crypto-agility in PQC Contributions to funded projects ARSENE Project-funded under PEPR Cyber-2022/2027 FORWARD project-funded under PTCC 2025/2029512/05/20