设计可靠的PTP基础设施：从PHC到SyncE和时钟稳定性.pdf

1、Skyworks Timing BUSean Liu Sr.Principal Application EngineerDavid Spencer Sr.Product Line ManagerDesigning Reliable PTP Infrastructure:From PHC to SyncE and Clock StabilityDesigning Reliable PTP Infrastructure:From PHC to SyncE and Clock StabilitySkyworks Timing BU Sean Liu-Sr.Principal Application

2、EngineerDavid Spencer-Sr.Product Line ManagerTIME APPLIANCES(TAP)Overview of ITU-T PTP+Synchronous Ethernet(SyncE)clock modelPros and cons of SyncE in term of PTP clock performanceMitigation scenario on SyncE installationSystem blocks on mitigation of SyncE Installation on PTP clockProcedures on the

3、 implementation of mitigationLab result analysis and comparisonOpen discussionAcknowledgment to the significant contribution from Andrew Kang of Skyworks AgendaITU-T PTP with SyncE Clock ModelITU-T SG15/Q13 defines two profiles using IEEE 1588 for timing distribution,and various clock-types associat

4、ed with each profileThe typical PTP combining SyncE usage simplified clock modelUsing SyncE can gain benefit for enhanced performance when PTP in holdover,reduce packet ratesThe drawback using SyncE,transient during to SyncE locking,lost,and re-lockingBut techniques exist to mitigate some of these d

5、rawbacksMitigation Scenario and System Blocks TimeClockFrequencyClockPLLPort 1Port 2PHCSyncE RecPTP stackServoESMCstackPTP timestamps/messagesESMC messagesSoC/PHYSyncE Recovered ClockDCO controlDSPLL control1PPSTS ClockSyncE Transmit ClockSyncE outputSoftwareThe scenario:PTP locked without valid Syn

6、cE,then SyncE available to be used as physical layer clockThe SyncE frequency is offset from the PTP timebasewhich lead to short term accumulation of time errorSoc/PHYPTP Hardware Clock(PHC),SyncE Clock Rx/Tx handlingPTP/ESMC packet injection and retrievalServo/StackPTP and ESMC stack,DPLL control a