测试采用芯片组构建的系统级封装.pdf

1、Speaker:Dr.Rajesh PendurkarContributors:Mike Bartley Alpinum,Boon Chong Ang Intel Corporation,Anand Muthaiah and YoganSenthilkumar Tessolve,Madhumita Sanyal and Aparna Tarde Synopsys,Rajesh Pendurkar Cadence,Frank Mileke Advantest,Dhanapathy Krishnamoorthy Intel,Wade Bick Teradyne,James Wong Palo Al

2、toElectronTesting Systems-in-Package built with ChipletsSiP Test ProblemKey IssuesTest Cost:Test InsertionsKGCThermal ProfileInterconnect TestDFT Architectures/Standards as SolutionsConclusionOutlineSystem in Package designs are growingOne bad die can cause the whole package to failChallenges in SiP

3、 testing:oHow do we build SiP in cost effective manner with Chiplets coming from different vendorsoHow to guarantee Structural Defect Coverage of the individual chiplets and get Known Good Chiplet(KGC)to achieve Known Good Stack(KGS)oCan we reuse of chiplet level tests at System Level(SLT)with use c

4、ase scenarios under varying load conditionsoHow do we get Individual Chiplets Test data be available for the final product company and exercise Repair Problem StatementChiplet Based SiPSoc with MonolithicSoC with 4 ChipletsYield Improvement1000 Parts1000 partsYield 70%Yield 85%21%at Cost of Testing

5、more chiplets1000*0.7=700 KGD1000*0.85*4=3400 3400/4=850 KGC850/700=1.21Comparisons of Test CostsMonolithic IC Cost Model(single manufacturing flow)Comparisons of Test Costs:Increased Test InsertionsMonolithic devices Chiplet Device devices System Level Test(SLT)and Functional TestSLT in SoC focuses

6、 on function to complement traditional structural testCan have an even bigger impact on chiplet testingChiplet/Multi-Die Systems andMonolithic Systems ComparisonParameterChiplet/Multi-Die SystemsMonolithic SystemsDie/Chip SizeSmaller individual die/chip sizesLarger monolithic die sizeYieldHigher yie