用于人工智能规模化网络的超低功耗MicroLED互连.pdf

1、Chris PfistnerAvicenaUltra Low Power microLED Based Interconnects for AI Scale Up NetworksUltra Low Power microLED Based Interconnects for AI Scale Up NetworksChris PfistnerAvicenaAI Networks Energy Efficiency and Bandwidth Density NeedsLLM outpacing memory bandwidth 100,000 xx 100,000Using optimize

2、d interconnect technology is absolutely critical!IT projected at 20%of world electricity by 2030Wide&Slow Architecture:Connecting Arrays of LEDs and Detectors with Fiber BundlesLab test of Avicenas LED arrayFrom LED display&camera sensor eco systemEach pixel running at data rates of 4 Gbps 16GbpsArr

3、ay size 400 Multi-terabit aggregate data rateActual LightBundle chipletRXTXRx:Camera SensorTx:LED displaymicroLED Transceiver Key Building BlocksLED ARRAY1PD ARRAY2OPTICAL FIBER4ASIC TXASIC RX5microLENSES3microLED Transceiver Key Building BlocksMicroLED Interconnects -Ideally Suited for Scale Up Net

4、works7Key Specs for Scale Up:ParameterPerformanceEnergy Efficiency*2Tbps/mmReach20mReliability 10 FIT*Optical Link including Driver,Laser/LED,PD,TIA,LALightBundle:1pJ/bit (NRZ format)2Tbps/mm(2D array)20m GaN LEDs:-very reliable-Op.Temperature:-55 to 125C-cost effectiveModular Architecture:1.6Tbps O

5、BO Module:12.8Tbps CPO Module:ShorelineOptional highspeed SerDes chiplet90 degree optical couplerOptical Tx&Rx chipletsBeach Front Density&Energy Efficiency against Link Distance1pJ/bit 1Tbps/mm10008Scale UpScale OutDARPA:Gordon KeelerLatest Technical Update:APD ReceiversTx Power with hybridTx Power

6、 with hybrid-bonded APD Rxbonded APD RxTSMC collaboration:CMOS Image sensor with low noise APDTSMC collaboration:CMOS Image sensor with low noise APDAPD key highlightsAPD key highlightsHybrid bonded to CMOS Rx logic dieHybrid bonded to CMOS Rx logic dieHighly linearHighly linearO