OCE 事务和链路层规范 1.2.pdf

1、Brian Murray,SoC Architect,VeriSiliconHelia Naemi,Technologist,Astera LabsOCE Transaction and Link Layer 1.2 Specification UpdateSERVER:OPEN CHIPLETECONOMYChiplet Die Disaggregation Any IP Protocols become chiplet interfaces Agnostic to chiplet architecture Transparent to softwareIndependent of Tran

2、sport Initial support for Bunch of Wires Future Universal TLL(U-TLL)mapping to any physical layerChiplet SiP=Monolithic SoC Once chiplet links are brought-up,the chiplet integration behaves like a monolithic SoCOCE Transaction and Link LayerA protocol stack for translating bus transactions across a

3、BoW interface between two chipletsTransport for a variety of busses and signalsFocus on simplicity,flexibility,and low latencyTransaction Layer maps SoC bus protocols(e.g.AMBA)to message packetsWide support that is easily extensibleLink Layer adds error protection(ECC)and breaks the messages into gr

4、anulesMaps varying width BoW“Mainband”interfacesBackground:1.0 Transaction and Link Layer1.2 Introduces a protocol stack that utilizes the BoW Sideband Slice that complements the Mainband Link LayerAddition of a BoW Sideband ProtocolAddition of a Link Control ProtocolGeneral fixes and clarifications

5、 in the Mainband link layer specificationNo functional changes to the existing textNo issues with compatibility with the 1.0 specOCE Transaction and Link Layer Specification 1.2BoW Sideband StackBoW Sideband ProtocolProvides a way to transmit and receive packetized memory mapped bus transactions ove

6、r a BoW Sideband Slice Link Control ProtocolRegister map and communication protocol for controlling the BoW Mainband PHY stateProtocol for BoW Sideband SlicesPacket format for memory mapped transactionsSupports variable data length,though packet size is fixedCommands Read,Read Response,Non-Posted Wr