P4新曙光.pdf

1、New Dawn of P4Deb Chatterjee,IntelWe continue to have a vibrant communityMany new membersCISCO is now another premium member along with Google and IntelDiscussion ongoing with several other companiesAcademic interest is still strongOpen sourcing of Tofino SW componentsList of P4-programmable devices

2、 expanding!Intel announced P4-programmable E2200(400 Gbps IPU)AMD/Pensando Salina 400 Gbps NICsXsight Labs X-Switch familyP4 programable FPGA productsAMD/Xilinx VitisNetP4Renewed interest in the reborn AlteraThis is in addition to existing Tofino installations(EdgeCore DCS 810 and others)and other P

3、4 devices So whats the bad news?Perceived headwindsMerchant ASIC roadmap and supply uncertaintyAccess Barriers(SDKs,NDAs,tooling)Toolchain fragmentationOperational skills and verificationCompeting paradigms Additional challenges brought by AI boomCompetition for silicon/investment bandwidthMismatch

4、of compute vs memory/resource constraintsDiverging design priorities(AI vs programmable packet processing)Ecosystem gravitation toward AI stacks“Black box”closed loop preference vs transparencyPotential misalignment in scaling and associated fear of obsolesceLots of new opportunities for P4Match/act

5、ion as the common HW abstraction for high-speed packet processing,with P4 as the enabler.Reduces Silicon respin risk compared to protocol-aware approachesP4 as the spec language(exemplary work by Steffen Smolka and others here)In-band Network Telemetry(INT/IOAM),postcard sampling,heavy-hitter&flowle

6、tdetectionP4 as the fast feedback plane for ROCE/UEC style RDMA transportsOpportunities in 5G/6G such as MEC service chaining with SRV6 SIDs in P4Long term betsP4 in in-network compute primitivesData sovereignty using P4Better resource utilization and load bal