7. 将RISC-V扩展至VLIWSIMD架构应对特定应用工作负载.pdf

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1、Extending RISC-V into VLIW/SIMD Architectures forApplication-Specific Workloads毛海雪,Staff Applications Engineer2025-07-18Legal DisclosureCONFIDENTIAL INFORMATIONThe information contained in this presentation is the confidential and proprietary information of Synopsys.You are not permitted to dissemin

2、ate or use any of the information provided to you without the prior written consent of an authorized officer of Synopsys.IMPORTANT NOTICEIn the event information in this presentation reflects Synopsys future plans,including but not limited to Synopsys financial targets,expectations and objectives;st

3、rategies related to our products,technology and services;business and market outlook,business opportunities and strategies;and more,such information is based on current estimates,provided as of the date of this presentation and are subject to change.Synopsys undertakes no duty to,and does not intend

4、 to,update any forward-looking statement,whether as a result of new information,future events or otherwise,unless required by law.2025 Synopsys,Inc.3OutlineISA extensibility in the RISC-V philosophyISA extensibility for high computational performanceExtending RISC-V into VLIW/SIMD architecturesASIP

5、Designer:a tool-suite to design extended RISC-V architectures1234 2025 Synopsys,Inc.4ISA Extensibility:a Key Ingredient of the RISC-V PhilosophyStandard ExtensionsProposed and developed in the RISC-V community for new areas of common interestCollaborative review and ratification processInceptionPlan

6、DevelopFreezePublic ReviewRatifiedIIntegerEReduced IntegerMInteger Multiply&DivisionAAtomicsFSingle-Precision Floating PointDDouble-Precision Floating PointGGeneralQQuad-Precision Floating PointC16-bit Compressed InstructionsBB ExtensionPPacked SIMDVVectorHHypervisorZAdditional Unprivileged Extensio