16-David-Kelf.pdf

1、Advanced RISC-V Core and SoC Verification Towards the Anticipated Certification RequirementsRISC-V Summit China 2024David Kelf,CEO,Breker Verification SystemsA Look At RISC-VOpen Instruction Set Architecture(ISA)gaining significant traction in multiple applicationsSignificant verification challenges

2、o Arm spends$150M per year on 1015verification cycles per coreo Hard for RISC-V development group to achieve this same qualityo Lots of applications expands verification requirementso Requires automation,reuse and new thinkingRISC-V International developing certification program to provide an assura

3、nce metric for RISC-V devices2 Breker Verification Systems,Inc.All rights reserved.RISC-V International CertificationRVI Certification Steering Committee(CSC)recently formed with the intent of increasing industry confidence in certified RISC-V cores and IPo Considered important as RISC-V gains in po

4、pularityCSC now working on test sources,process plans,etc.o May look to commercial entities to provide rigorous certification testsBreker involved as our SystemVIPs are aligned with potential CSC tests Breker Verification Systems,Inc.All rights reserved.Breker Systems Confidential3Core/IP DeveloperP

5、rocessor&System ComponentsSoC DeveloperProduct DeveloperEnd DemandersSupply ChainCertificate DemandCertificateCertificateCertificateMeeting RISC-V Verification ChallengesReuse&automation to meet quality expectationo Automated test generation keyRISC-V special requirementso Custom instruction verific

6、ationo Compliance assuranceo Broad range of architecturesDifferent processors have different needso Embedded coreso Processor clusterso Application processors4ComplexityUp&running“Hello World”ISA architectural complianceMicro-architecture functionality System integration integrityPerformance/power p