10-刘禹.pdf

1、PySpike:Python Bindings of RISC-V ISA SimulatorLIU Yu1,2TAN Min-Qiang1YU Zhi-Hong1,B1Wu-Xi EsionTech Inc.2HuiMt LabsRISC-V Summit China,2024Y.Liu,M.Tan,Z.Yu(EsionTech Inc.&HuiMt Labs)PySpike:Python Bindings of RISC-V ISA SimulatorRVSC 20241/9Who we are,and what we doEsionTech Inc.subsidiary of CETCs

2、 Research Institute 58,founded in 2013;headquarter in Wuxi,R&D centers in Beijing,Shanghai,Wuhan,.;vendor of all-programmable and heterogeneous computing chips;new to RISC-V ecosystem,since early 2023;HuiMt Labsaffiliated with EsionTechs Beijing R&D Center;small group of open-source software enthusi

3、asts;veterans in HW/SW co-simulation and co-verification tools;contributors to RISC-V tools,i.e.spike,riscv-dv,.;Y.Liu,M.Tan,Z.Yu(EsionTech Inc.&HuiMt Labs)PySpike:Python Bindings of RISC-V ISA SimulatorRVSC 20242/9What Spike is all aboutDe facto standard RISC-V ISA simulator,aka.Spike reference mod

4、el for differential testing in constrained-random verification;C+code base(40k+lines),14+years of history,and state-of-the-art ISA support;command line tools(spike,xspike,spike-dasm,.)and C+libraries(libriscv,.);plugin system based on dynamic loading(dlopen)of shared objects/libraries;RISC-VISA Simu

5、latorRISC-VRTL DesignRTL TraceISS TraceTestGeneratorRISC-V ELFTraceAnalyzerReportiterative alignmentY.Liu,M.Tan,Z.Yu(EsionTech Inc.&HuiMt Labs)PySpike:Python Bindings of RISC-V ISA SimulatorRVSC 20243/9What Spike is all aboutDe facto standard RISC-V ISA simulator,aka.Spike reference model for differ

6、ential testing in constrained-random verification;C+code base(40k+lines),14+years of history,and state-of-the-art ISA support;command line tools(spike,xspike,spike-dasm,.)and C+libraries(libriscv,.);plugin system based on dynamic loading(dlopen)of shared objects/libraries;spikeCommand Line ToolsC+Li