004--李盼.pdf

1、2024 RISC-V Summit ChinaRVV Auto-Vectorization in GCCPan Li IntelLiu,Hongtao-IntelIntel ConfidentialDepartment or Event Name2RISC-V Summit China 20242Legal Notices and DisclaimersStatements in this document that refer to future plans or expectations are forward-looking statements.These statements ar

2、e based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements.For more information on the factors that could cause actual results to differ materially,see our most recent earnings relea

3、se and SEC filings at .All product plans and roadmaps are subject to change without notice.Any forecasts of goods and services needed for Intels operations are provided for discussion purposes only.Intel will have no liability to make any purchase in connection with forecasts published in this docum

4、ent.Code names are often used by Intel to identify products,technologies,or services that are in development and usage may change over time.No license(express or implied,by estoppel or otherwise)to any intellectual property rights is granted by this document.Intel Corporation.Intel,the Intel logo,an

5、d other Intel marks are trademarks of Intel Corporation or its subsidiaries.Other names and brands may be claimed as the property of others.This document contains information on products and/or processes in development.Intel ConfidentialDepartment or Event Name3RISC-V Summit China 20243AgendaScalabl

6、e/FixedAdvanced VSETVLDynamic LMULConditionalRoundingAdvanced FRMEarly Exit(GCC-15)Saturation ALU(GCC-15)More in GCC-15 for Auto-VectorizationIntel ConfidentialDepartment or Event Name4RISC-V Summit China 20244Scalable(default)by RiVAI,Ventana Micro and IntelAny vlen is a multiple of zvl bits.-mrvv-