5.Scaling out RISC-V systems for HPC_SiFive Arteris joint presentation.pdf

1、RockyZhangPrincipal Engineer,Field Application,SiFiveScaling out RISC-V systems for HPCCunrongFengSenior FAE managerArteris23Interesting Work on RISC-V Hardware Presented in late 2024Check out full presentation here4What is RISC-V Bringing to HPC?ControlDevelopmentDirectionCustomizableFeatureSetCorr

2、ectHardwareChoiceExplorationandExperimentationPreciseFunctionalityBespokeFeatures5Fundamentally,HPC Loves OpenOpen Hardware StandardsRVA23 hardware is coming!China is driving a significant amount of this effortOpen-Source SoftwareCanonical focusing on RVA23 for its next Long-term releaseAvailability

3、 of RedHat developer edition enables developers to create and optimize apps nowOther foundational elements like Ceph,SLURM and OpenMPI at various stages of release and validation on RISC-V platformsOpen Programming ModelsOneAPISYCLRISC-V;One architecture to span Scalar,Vector and Matrix compute6Dot-

4、ProductAll state held in existing vector registersBatchedDotProductAll state held in existing vector registersVME-Vector-Matrix ExtensionsOuter-Product matrix-multiply operationsNew matrix state for accumulated resultsSources for computation come from existing vector registersIME-Integrated Matrix E

5、xtensionsInner-Product matrix-multiply operationsAll state held in existing vector registersAME-Attached Matrix ExtensionsOuter-Product matrix-multiply operationsNew state defined for sources and destinationDoes not rely on vector extensionOther operations defined(e.g.-activations,requantization,nor

6、malization)can be performed without vector extensionCustomers can harness common software base and apply across different compute resources based on performance,power and cost constraintsKeyFeaturesDecodewidth6-wide OoO 64-bit coresISARVA23 compliant(RISC-V Vectors and Vector Crypto)Cache64KB L1$and