用于忆阻器辅助逻辑综合的岛式多目标进化框架.pdf

1、1An Island-Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided LogicUmar Afzaal,Seunggyu Lee,and Youngsoo ShinSchool of Electrical Engineering,KAIST,KoreaOutlineIntroductionMotivationProposed methodExperimental resultsSummary23Logic OperationConventional method is executed

2、within a processing unit(CPU,GPU)Processed data is transferred to the memory for storageData transfer degrades both performance and energyProcessing-in-memory(PIM)enables logic operations to be performed within the memoryData transfer is significantly reducedRepetitive operations(e.g.,machine learni

3、ng model)on large dataset can be accelerated4Memristor for PIM Logic OperationNon-volatile resistive memory(memristor)is leveraged for PIM logic operationMemristor offers low(or high)resistance state for logic-1(or-0)Resistance state is determined by applied voltage(V):switching to low resistance st

4、ate(LRS):remaining current resistance state(CRS):switching to high resistance state(HRS)5PIM Logic OperationLogic synthesisIn-memory mappingAfter logic synthesis,in-memory mapping is performed TCAS-ILogic function is synthesized into 2-input NOR and INV netlist#Nodes of AND-INV graph(AIG)is reducedE

5、ach gate of netlist is mapped into memristive crossbar array Gate input and output are stored in distinct memristorsAll memristors for gates should be aligned either in a row or a columnEach gate is operated in one clock cycleMultiple gates can be computed in the same clock cycle parallel operationA

6、ll input memristors are aligned,along with their corresponding output memristors6In-Memory MappingParallel operation of 1 and 2Copying a value from one memristor to another can be executed copy operationTwo INV operations are performed in two clock cycles#Copy operations depends on mapping methods7I