标准单元布局生成：回顾、挑战和未来工作.pdf

1、Standard Cell Layout Generation:Review,Challenges,and Future WorksChung-Kuan Cheng,Byeonggon Kang,Bill Lin,Yucheng WangDept.of Computer Science and EngineeringUniversity of California San Diego30th Asia and South Pacific Design Automation ConferenceASP-DAC 2025Outlines1/141.Motivation2.Review:Placem

2、ent and Routing with Tool Sets3.Challenges:Complexity and Optimality4.Future Works:Optimization and New Devices5.ConclusionMotivation:Relentless Demand for Scaling2/14 Standard cells are one pivotal brick for chip power,performance,and area(PPA)scalingIMEC logic scaling loadmapMotivation:Standard Ce

3、ll Design Flow NP-complete with limited problem sizes3/14Review:Cell Layout Automation Cell generators for sub-10nm node covering placement and routing4/14Challenges:Complexity&Optimality Transistor Partitioning Reduces the search space Misses the best solutionDesign hierarchy based partitioningFast

4、/Not optimal 5/14Exhaustive searchSlow/Optimal Challenges:Complexity&Optimality Gear Ratio&Offset More routing resources with added complexity E.g.2:3 GR spans a non-uniform grid6/14Challenges:Complexity&Optimality Design Trade-offs Cell Area vs Pin accessibilityBetter pin accessibilityBigger area7/

5、14Worse pin accessibilitySmaller areaFuture Works:Optimization&New Devices8/14 Logic Optimization Expand search space for optimality Produce multiple design possibilities9/14Future Works:Optimization&New Devices Topology optimization-1 Internal net state verification for transistor removal Changing

6、stack order for better Euler path10/14Future Works:Optimization&New Devices Topology optimization-2 Increasing the drive strength of cell differently Net splitting can improve circuit performance11/14Future Works:Optimization&New Devices Standard cell fusion P