1、PROCESSING-NEAR-MEMORY WITH CHIP LEVEL 3D-ICMIAO LIUBRIAN LI ON BEHALF OF MIAO LIUMIAO LIU,DAVID WEI ZHANG,QINGQING SUNFUDAN UNIVERSITY,SHANGHAI,CHINAAGENDAIntroduction3DIC RoadmapSRAM-on-Logic Partitioning2D vs 3D Area BenchmarkingSRAM-on-Logic ImplementationSRAM-on-Logic AdvantageSRAM-on-Logic Cha
2、llengeConclusionINTRODUCTIONIssues:Solution Demo CaseMoore Law hard toproceedBandwidth demanding from AI/AutomotivePower limitationCost limitation3DICCA787nmSRAM&Logic Separation3D Implementation&SignOff3DIC ROADMAPFan-Out Wafer Level Package(FOWLP)3DIC ROADMAPChip-Level 3D:DRAM-on-Logic3DIC ROADMAP
3、Chip-Level 3D:SRAM-on-Logic3DIC ROADMAPTrendINFO/FOWLPDRAM-on-LogicSRAM-on-LogicLogic-on-Logic2018Mature technology in various applications2021Mining machine Chips2022Advanced Multi-Core CPU/XPU2024AI Chips3.5DSRAM-ON-LOGIC PARTITIONINGLogical PartitionSRAM-ON-LOGIC PARTITIONINGFeedthrough Insertion
4、SRAM-ON-LOGIC PARTITIONINGMulti-fanout Port Cloning2D VS.3D AREA BENCHMARKINGSRAM Die Layout2D VS.3D AREA BENCHMARKING2D vs.3D die edge lengthLogic Length Logic area array_x array_space mem_x mem_y mem_areatotal_use_area2D Length1540237160055.3151109.8872.09 967845.4823339445.48218271560243360055.31
5、51109.8872.09 967845.4823401445.48218441580249640055.3151109.8872.09 967845.4823464245.48218611600256000055.3151109.8872.09 967845.4823527845.48218781620262440055.3151109.8872.09 967845.4823592245.48218951640268960055.3151109.8872.09 967845.4823657445.48219121660275560055.3151109.8872.09 967845.4823
6、723445.48219301680282240055.3151109.8872.09 967845.4823790245.48219471700289000055.3151109.8872.09 967845.4823857845.48219641720295840055.3151109.8872.09 967845.4823926245.48219811740302760055.3151109.8872.09 967845.4823995445.4821999SRAM-O