FTAFP：用于大规模SoC分层设计的馈通感知平面规划器.pdf

1、FTAFP:A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCsZirui Li1,*,Kanglin Tian1,*,Jianwang Zhai1,Zixuan Li1,Shixiong Kai2,Siyuan Xu2,Bei Yu3,Kang Zhao11Beijing University of Posts and Telecommunications2Huawai Noahs Ark Lab3The Chinese University of Hong KongJan.21,20251O

2、utline Introduction Preliminaries Framework Evaluation Conclusion2IntroductionBackground As the scale and complexity of System-on-Chips(SoCs)continue to grow,hierarchical and modular concepts pushing the floorplanning challenge down to the sub-chip level.Hierarchical breaks complex systems down into

3、 multiple levels of subsystems,modular design to package and reuse different functionalities at each level.These integrated,bottom-up design methods significantly speed up the front-end chip design process.3IntroductionChallenge However,these methods also present new optimization challenge in floorp

4、lanning,named Feedthrough.Feedthrough is a through-module connection,yet it would require additional buffers and ports inside the module for data transmission.Fig.1.The violations caused by feedthrough insertion in hierarchical floorplanning of the large-scale SoC.4IntroductionRelated works Analytic

5、al-based Methods1 Generally adopt a two-stage framework of global distribution and legalization.Heuristic Methods2 Rely on topological representations and employ heuristic algorithms to optimize floorplans.Learning-based Methods3 learning an optimized and generalized mapping between circuit connecti

6、vity to produce a chip floorplan._1F.Huang,et al.“Handling orientation and aspect ratio of modules in electrostatics-based large scale fixed-outline floorplanning,”In:Proc.ICCAD,2023.2Y.-C.Chang,et al.“B*-Trees:a new representation for non-slicing floorplans,”In:Proc.DAC,2000.3Y.Liu,et al.“GraphPlan