HAMMER：通过运行时可重构 CGRA 实现硬件感知的运行时程序执行加速.pdf

1、HAMMER:Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAsQilin Si,and Benjamin Carrion SchaeferQilin.siutallas.edu,schaferbutdallas.edu30thAsia and South Pacific Design Automation ConferenceASP-DAC 2025Department of Electrical and Computer EngineeringJanuary 2

2、1,2025,Tokyo23 Similar electronic systems have different components.E.g.,low-end vs.high-end carsWhat Runtime hardware-aware architecture and design flow that is able to automatically accelerate compiled programs based on underling hardwareWhy Reduces development time(design and verification)How Map

3、 accelerators to Coarse-grain Reconfigurable array which his programmed with accelerator based on runtime detection of piece of SW which can be acceleratedMotivationHW dependent re-write1:-2:-3:-:N:-(Cin)ApplicationC1C2+HW extensionsCzCHWaccCompile(e.g.,msp430-gcc,msp432-gcc)Compile(custom compiler)

4、Low-end car with simple electronic system High-end car with complex electronic systemSource code verification High-Level Synthesis Design circuits using software languages Definition:“Automatic conversion of a behavioral,untimed description into efficient hardware that implements that behavior”Benef

5、its1.Software programmability and hardware performance2.Faster verification3.Decouples functionality from implementation allows to easily re-target any behavioral description to new technologies and newer design constraints(i.e.,area,power,performance)High-Level SynthesisANSI-C/C+/SystemCHigh-Level

6、SynthesisLogic SynthesisPlace and RouteAreaLatencyPowerGDSIITechlibTarget freqSWaP-CHigh-Level Synthesis in Practice#define pragma1 array=reg#define pragma2 loop=all#define pragma3 loop=alltechlibHLS(ASIC,FPGA)Cin(ANSI-C/C+/SystemC)#include”pragma.h”int buffer16;/pragma1/pragma2for(i=7;i0;i-)bufferi