CPONoC：片上光网络的关键路径感知物理实现.pdf

1、CPONoC:Critical Path-aware Physical Implementation for Optical Networks-on-Chip1Department of Electrical Engineering,National Taiwan University of Science and Technology,Taipei,Taiwan2Department of Electronic Design Automation,Technical University of Munich,Munich,Germany1Yan-Ting Chen1,Zhidan Zheng

2、2,Shao-Yun Fang1,Tsun-Ming Tseng2,and Ulf Schlichtmann2Jan.23,2025Outline1.Introduction2.Methodology3.Experimental Results4.Conclusions 21.INTRODUCTION 2.METHODOLOGY 3.EXPERIMENTAL RESULTS4.CONCLUSIONS 3Optical Networks-on-Chips(ONoCs)A 3-D stacked multicore processor 4-INTRODUCTION-Off-chip memoryP

3、hotonic layerElectronic layerClusters of processorsM0M2M1M3H0H2H1H3Array of off-chip lasers1234TSVTSVTSVTSVMemory controllerHubMicro-Ring Resonator(MRR)The working principle of MRRPhotonic switching element(PSE)5-INTRODUCTION-Global and detailed routing 12,Huang-Yu Chen、Yao-Wen Chang =MRRMRROff-stat

4、eOn-stateWavelength Routed ONoC(WRONoC)Two Types of Classifications for the WRONoCTopological designPhysical implementation 6-INTRODUCTION-s2m2m3m4s1m1s3s41212231213311322s2s3s4m1 m2m3m4s1Insertion LossInsertion loss in an optical router is caused byPropagation lossCrossing loss Bending lossDrop los

5、sWhere L,C,D,B separately represent the waveguide length,the number of waveguide crossings,the number of MRR drops,and the number of waveguide bends in p7-INTRODUCTION-Related WorkTopological design-Router Briere et al.,DATE07GWOR Tan et al.,SOPO11Light Zheng et al.,ASP-DAC21Physical Implementation

6、PROTON+Beuningen et al.,ACM15PlanarONoC Chuang et al.,DAC18ToPro Zheng et al.,CAD218-INTRODUCTION-routerLightPlanarONoC Chuang et al.,DAC18Based on Hamiltonian cycle finding9-INTRODUCTION-Cons of PlanarONoCCritical path causing the maximum insertion loss is not addressed10-INTRODUCTION-M0H1M1H0PSE2P