20250122_E-103_Nikoukary.PDF

1、Applying Co-Design/Co-Verification to Multi-Die Designs That Use Advanced PackagingShawn Nikoukary,Sr.Dir.Adv.PackagingJanuary 2025 2025 Synopsys,Inc.2Agenda&Topics Advanced Packaging Design-Team Challenges Architecture/Partitioning and Layout implementation High-Capacity Simulations and sign-off Au

2、tomation to address challenges2 2025 Synopsys,Inc.3Advanced Packaging Design ChallengesFaced by the Design team(there are many other challenges faced by other teams:)Lets start by establishing that every Advanced Package design is different.Same design goes from CoWoS-S CoWoS-L OSATEcosystemArch&Des

3、ignSim&Sign-OffEstablishing partnership with suppliers and foundriesManaging design rules,techfiles and PDKs/ADKsCertification/Qualification,etcDesign PartitioningMega-Design CapacityChip-Design flow/toolsChip-Design sim tools new to packaging SI/PI teamSign-Off process and methodologiesOur focus fo

4、r today 2025 Synopsys,Inc.4Architecture and Layout 4SOC Design Partitioning(PPP):RTL co-optimization+1.IPs 2.Die Size 3.Floorplan 4.SI/PI 5.Thermal Technology Node Selection Interface IPs Die Size Packaging Technology Floorplan Thermal SIP/PI Physical Design of Massive Layouts 10s of thousands of ne

5、ts to route(ie.UCIe&HBM)100s of power domains(patterns planning,routing,optimizing)10s of millions of ubumps,C4s and BGAs Chip-design platform instead of PCB layout toolsChallenges to Advanced packaging teams:Need to be involved with chip-design process Rapidly evolving-tools and methodologies Need

6、to be simulated co-designed and optimized*New to most packaging teamsEngineers with different skillsetsNew Design MethodologiesNew Tools(auto routers)+Hopefully,you have not donated your university book for Verilog 2025 Synopsys,Inc.5Simulation&Sign-OffAdvanced packages,unlike substrates need to go