20250122_E-103_Caglar.PDF

1、Extending Verification&Validation to Multi-Die DesignsChiplet Summit 2025Levent Caglar,Executive Director HPC,AI,Data Center Solutions1/22/2025 2025 Synopsys,Inc.2Pervasive AI Drives New Design ParadigmsThe Need for Hardware Scaling Leads to New Architectures and Design ApproachesWide range of optim

2、izations&innovationsSource:AI and Memory Wall:2403.14123(arxiv.org)20122013201420152016201720182019202020212022202320242025P100H100TransformerSwitchTransformerHW FLOPS Moores LawTransformer Size:410 x/2yrsHW FLOPS:3.0 x/2 yrsAI HW Memory:2x/2 yrsMoores Law:2x/2 yrsDRAM Bandwidth:1.6x/2 yrsInterconne

3、ct Bandwidth:1.4x/2 yrsAI HW MemoryTransformer SizeInterconnect BWDRAM BWLog ScalePCIe 3.0NVLink1.0PCIe 5.0GDDR5HBMHBM2HBM2eSource:Baya Systems EETimes Chiplet Summit 2025 Synopsys,Inc.3New Dimensions in Architecture Exploration SoC-level macro-architecture decisions HW/SW partitioning IP selection,

4、configuration,and connectivity Interconnect/memory dimensioning System-level power analysis Additional multi-die macro-architecture decisions 2025 Synopsys,Inc.4GPU ChipletCPU ChipletAI/ML ChipletSensor I/F ChipletSystem&Connectivity ChipletCPUClusterAI AcceleratorNetwork On ChipSafetyManagerGPUClus

5、terSensorFusionSensor InterfacesVisionDSPISPCodecsSystem InterfacesMemoryController&InterfacesDie-to-Die I/F*Die-to-Die I/F*Die-to-Die I/F*Die-to-Die I/F:High Speed,Low Distance,Low EnergyDie-to-Die I/F*Optimizing Architectural Functions into Chiplets 2025 Synopsys,Inc.5Sign-OffPhysical DesignSoC/Mu

6、lti-Die DVEmulationArchitecture Modeling with RTL Simulation and Emulation for Performance and Power Verification IP/Subsystem DVSimulationSemiconductor Design and Verification FlowPerformance and Power Modeling&OptimizationProductRequirementsImplementation SpecificationRTL,UPFSWIP-level PPAsystem p