Lunar Lake：驱动下一代人工智能电脑.pdf

1、Lunar Lake Architecture SessionHotChips 2024Arik GihonSenior Principal Engineer,CCGSoC ArchitectureBreakthrough x86 power efficiencyMassive leap in graphicsUnmatched AI computeExceptional core performanceFlagship SoC for the next gen of AI PCsLunar LakeUp to 40%lower SoC power*Similar ST perf at hal

2、f the power*Up to 1.5X better graphics*Up to 120 platform TOPS*Versus Intels previous gen.For more information,go to I tilePlatform Controller tileFiller tileBase tileFoverosPackageMemoryCompute tilePlatform Controller tileBase tileStiffenerFoverosBuilt with advanced packagingLunar Lake Construction

3、Up to 32GBwith 2 ranksUp to 8.5GT/sper chipSupport forLPDDR5xDRAM Support for16b x4 channels Up to 40%lower PHY powerUp to 250mm2 area savings First ever Intel integrationonto packageMemory onPackageArchitecture overviewLunar LakeCompute TileCompute tile structureCompute tile structureMemory side ca

4、cheMemory side cacheEnhanced EEnhanced E-core clustercore clusterNew power delivery&New power delivery&management management Platform Controller TileArchitecturalFrameworkLunar Lake Compute TileMonolithic die,on a leading processMonolithic die,on a leading processEnhancedSoC StructureFor better perf

5、ormance efficiencyCompute tile structureCompute tile structureNew NOC,with enhanced cachingNew NOC,with enhanced cachingOptimized memory latencyOptimized memory latencyGPUNPUIPUP-coreMediaDisplayP-coreP-coreP-coreE-coreE-coreE-coreE-coreNOCMemory PHYLunar Lake Compute TileMemory Memory Side Side Cac

6、heCacheMemory Side CacheFor efficient performance&lower power consumption for other enginesMemory side cacheMemory side cacheReduce DRAM traffic and powerReduce DRAM traffic and powerEnhanced both latency and bandwidth Enhanced both latency and bandwidth Caching for IO engines Caching for IO engines