13-Valtrix_Complexities of RISC-V Functional Verification.pdf

1、www.valtrix.inTony Wang王浩为王浩为August 23-25,2023RISC-V Summit ChinaAddressing the Complexitiesof RISC-V Functional Verification解决RISC-V功能验证中的复杂性www.valtrix.in1.Valtrix-EDA company headquartered in Bangalore,India;2.Developing products/solutions for CPU/SoC verification3.STING-First commercially availa

2、ble and most advanced design verification solution for RISC-V4.Software-driven portable self-checking architecturally correct stimulus generator5.Used by several RISC-V CPU/SoC companies such as Google,Seagate,Sifive and Tenstorrent for verifying functional correctness and architectural compliance o

3、f designsValtrix-An Introduction 简介www.valtrix.in01Challenges in RISC-V Design VerificationRISC-V 设计验证中的挑战02Challenges imposed by DUT ConfigurationDUT配置带来的挑战03Popular Test Generation Methodologies现行有效的测试生成方法04Functional Correctness and Compliance功能正确性和合规性功能正确性和合规性Agenda Of The Talk 议程05Test Generati

4、on over Design Life-Cycle在设计周期不同阶段的测试生成方法06Case Studies for Test Generation案例研究07Conclusion结论www.valtrix.inCPU/SoC Verification Challenges传统芯片验证中会遇到的挑战1.How many tests to run to ensure comprehensive verification?2.How to distribute the testing across simulation,emulation,FPGA and silicon for best th

5、roughput?3.How to write test stimulus which is portable across all DUT environments?4.How to debug failures from silicon quickly on simulations?5.How to develop a test which runs on simulation and silicon alike?6.How does test generation scale from top-level simulation test benches all the way to a

6、complete SoC on silicon?www.valtrix.inUnique Challenges in RISC-V VerificationRISC-V验证中独有的挑战1.Plug and play extension architecture leads to huge number of designs which need to be verified即插即用的扩展架构导致大量验证需求RV32I+MRV32IM+MRV32IMC+MRV32IMAC+MRV32IMAFDC+MRV32IMAFDCV+MRV32IMAFDCV+MRV32IMAFDCV+MURV32IMAFD