A Chiplet based SmartNIC Platform using Bunch-of-Wires.pdf

1、A Chiplet Based SmartNICPlatform using Bunch of Wires(BoW)ChipletsA chiplet based SmartNICplatform using BoWSuresh SubramaniamAdvanced Packaging and Systems Apex SemiconductorsChiplets are Thriving!Source:AMD FAD22Source:NextPlatformSource:NVIDIAHow to build a System of Chiplets outside of verticall

2、y integrated companies today?EcosystemNext-gen Disruptive SmartNICHigh Performance RISC-V CPU5D2D PHY with easy portability across fab&process nodesChiplet Design and System IntegrationCadence Integrity3D-IC PlatformTop-Level Planning3D P&R&Sign-OffAnalog/RFPackagingElectrical/ThermalIntegritySystem

3、 PlannerInnovus3D-ICVirtuoso/RFAllegroSigrity,Clarity,CelsiusMixed-Technology,Multi-Domain Common Hierarchical DatabaseDigital Silicon StackingEarly-StageThermal/Power AnalysisTop-Level Aggregation and OptimizationRF ModuleCo-Packaged OpticsLaminate SiP/MCMFOWLPInterconnect BridgeRDL InterposerCISSi

4、licon(TSV)interposerPre-&Post-Route Signal Integrity Chiplet-to-Chiplet Compliance3D Electromagnetic ExtractionSystem-Level Thermal AnalysisAnalog/RF StackingCase Study:Smart NIC PlatformCase Study:Smart NIC PlatformSmartNICPlatform ComponentsSmartNIC Hub(5nm)D2DD2DETHPCIe/CXLIOPCIe/CXLIORISC-V(5nm)

5、D2DIORISC-V(5nm)D2DIOAn Example Configuration on Organic SubstrateSmartNIC HUB ChipletRISC-V Chiplet1 TbpsD2D(BoW-256)x8 112Gbps Ethernetx32 PCIe Gen5/CXL 2.0GPIONetworking functions1 TbpsD2D(BoW-256)GPIO16 cores coherent through HubMEMSW StackReference FW and DriversPF and VF for Kernel and User Mo

6、deSiP is the new MotherboardChiplet Hub is the Queen of the SiP-Deimos Chiplet HubHubProcessorsMemoryAcceleratorsIO Configurable architecture that spans from Edge to Cloud Applications by number and type of chipletsconnected Composable with number of Hubs x number of Chipletsconnected per Hub Proces